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Multiply and accumulate unit using vedic multiplier

In normal multipliers delay will be more and the number of computations also will be more.

Vedic Multiplier in VLSI for High Speed Applications

Because of that speed of the circuits designed with the normal multipliers will be low and it will consume more power. The Vedic multiplier is designed by using UrdhavaTriyagbhayam sutra and the adder design is done by using reversible logic to perform high speed operations. Reversible logic gates are also the essentialconstraint for the promising field of Quantum computing.

The UrdhavaTriyagbhayam multiplier is used for the multiplication function to reduce partial products in the multiplication process and to get high concert and less area.

The reversible logic is used to get less power.

Vedic Mathematics Based Multiply Accumulate Unit

International Journal of Engineering Trends and Technology. International Journal of Scientific and Research Publications. High speed energy efficient ALU design using vedic multiplication techniques. Nivas AS, Kayalvizhi N. Implementation of power efficient vedic multiplier. International Journal of Computer Applications. Abdelgawad A, Bayoumi M. International Conference on Communication Technology and System. Designing an ultra-highspeed multiply-accumulate structure.

Highspeed and area efficient vedic multiplier. Reversiblelogic design with online testability. A review on reversible logic gates and their implementation.

FPGA implementation of high speed Vedic multiplier

High speed ASIC design of complex multiplier using vedic mathematics. A Novel design for high speed multiplier for digital signal processing applications Ancient Indian Vedic mathematics approach. International Journal of Technology and Engineering. Implementation of RISC processor for convolution applications.

International Journal of Computer Trends and Technology. Design and implementation of low power multiplier using vedic multiplication technique. International Journal of Computer Science and Communication. Motilal Banarsidass Publishers Pvt. Logical reversibility of computation. Efficient approaches for designing reversible Binary Coded Decimal adders. Novel high speed vedic mathematics multiplier using compressors. Reverse logic gate and vedic multiplier to design 32 bit MAC unit.